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LR38266
LR38266
DESCRIPTION
The LR38266 is a CMOS digital signal processor for color CCD camera systems of 270 k/320 k/410 k/470 k-pixel CCD with complementary color filters.
Digital Signal Processor for Color CCD Cameras
FEATURES
* Designed for 270 k/320 k/410 k/470 k color CCDs with Mg, G, Cy, and Ye complementary color filters * Switchable between NTSC and PAL modes * External performance control * Variable GAMMA and KNEE response * 8 to 10-bit digital input * Analog Y&C output by built-in 8-bit 2 ch DA converter * Switchable between Y, U/V (16 bits) and U/Y/V/Y (8 bits) digital video output * Line-lock and external lock function * CPU interface input/output * Accumulator to control auto exposure and auto white balance * Single +3.3 V power supply * Package : 100-pin LQFP (LQFP100-P-1414) 0.5 mm pin-pitch
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LR38266
PIN CONNECTIONS
100-PIN LQFP
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND VDD MCO1 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 VDD GND SDI SCK SLDI GND ENC
TOP VIEW
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ACL ADI0 ADI1 ADI2 ADI3 ADI4 VDD GND ADI5 ADI6 ADI7 ADI8 ADI9 GND VDD OCP1 CSYN GND CKI1 CKI2 GND CKI0 GND HP VD
76
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD1 DOC EOO VDD GND DCK1 YO7 YO6 YO5 YO4 GND VDD YO3 YO2 YO1 YO0 VREF DA GND DA VDD IREF2 IREF1 VB2 VB1 CENCO YENCO
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VRI GND FI CBLK CSYO VDD GND TST1 TST2 TST3 TST4 DCK2 GND CO0 CO1 CO2 CO3 GND VDD CO4 CO5 CO6 CO7 TST5 TST6
(LQFP100-P-1414)
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50
LR38266
BLOCK DIAGRAM
YOUT [7 : 0] ADI [9 : 0] OBCP 1H, 2H DELAY LINE LUMINANCE SIGNAL PROCESS
DAC
YENCO, VB1
CKI0, CKI1 CKI2, ENC VREF IREF1, IREF2 ADD [6 : 0] SDI, SCK, SLDI DATA [7 : 0] MICROCOMPUTER INTERFACE SSG COLOR SIGNAL PROCESS COUT [7 : 0]
DAC
CENCO, VB2
HP, CSYO, HD1 DCK1, DCK2 CSYN, OCP1, VD, FI CBLK, EOO, VRI DOC
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LR38266
PIN DESCRIPTION
PIN NO. SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ACL ADI0 ADI1 ADI2 ADI3 ADI4 VDD GND ADI5 ADI6 ADI7 ADI8 ADI9 GND VDD OCP1 CSYNC GND CKI1 I/O ICU IC IC IC IC IC - - IC IC IC IC IC - - O O - IC ADI0 to ADI9 are digital signal inputs. ADI0 is LSB. ADI9 is MSB. A grounding pin. Supply of +3.3 V power. Optical black clamp pulse output. Composite synchronous pulse output for analog video output. A grounding pin. Clock input. The frequency is below for each CCD. 270 k, 410 k CCD : 14.31818 MHz 320 k, 470 k CCD : 14.1875 MHz Clock input. The frequency is below for each CCD. 20 21 22 23 24 25 26 27 28 29 30 31 32 CKI2 GND CKI0 GND HP VD VRI GND FI CBLK CSYO VDD GND IC - IC - O O ICS - O O O - - 270 k CCD : 9.5454 MHz 410 k CCD : 14.3181 MHz 320 k CCD : 9.4583 MHz 470 k CCD : 14.1875 MHz ADI0 to ADI9 are digital signal inputs. ADI0 is LSB. ADI9 is MSB. Supply of +3.3 V power. A grounding pin. POLARITY DESCRIPTION All reset input. The internal circuit is initialized at power-on with a capacitor of 0.01 F.
A grounding pin. Clock input. The frequency is below for each CCD. 270 k, 410 k CCD : 28.6363 MHz 320 k, 470 k CCD : 28.3750 MHz A grounding pin. Horizontal drive pulse output. Vertical drive pulse output. Vertical reset input. Built-in vertical counter is reset by a low-input of more than one horizontal period. A grounding pin. Field index pulse output. Composite blanking pulse output. Composite synchronous pulse output. Output timing is variable by output mode. Supply of +3.3 V power. A grounding pin.
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LR38266
PIN NO. SYMBOL 33 TST1 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 TST2 TST3 TST4 DCK2 GND CO0 CO1 CO2 CO3 GND VDD CO4 CO5 CO6 CO7 TST5 TST6 YENCO CENCO VB1 VB2 IREF1 IREF2 DA VDD DA GND VREF YO0 YO1 YO2 YO3 VDD GND YO4 YO5 YO6 YO7 I/O ICD ICD ICD ICD O - TO TO TO TO - - TO TO TO TO ICD ICD DAO DAO DAO DAO DAO DAO - - DAI TO TO TO TO - - TO TO TO TO POLARITY DESCRIPTION Test input. Connected to low or open. Test input. Connected to low or open. Test input. Connected to low or open. Test input. Connected to low or open. Clock output for digital COUT. A grounding pin. 8-bit digital color signal output. CO0 is LSB. CO7 is MSB. A grounding pin. Supply of +3.3 V power. 8-bit digital color signal output. CO0 is LSB. CO7 is MSB. Test input. Connected to low or open. Test input. Connected to low or open. Analog Y signal output. Analog C signal output. Bias voltage output of built-in DA converter, connected to GND through a capacitor. Bias voltage output of built-in DA converter, connected to GND through a capacitor. Bias current output of built-in DA converter, connected to GND through a resistor. Bias current output of built-in DA converter, connected to GND through a resistor. Supply of +3.3 V power input for built-in DA converter. A grounding pin for built-in DA converter. Bias voltage input of built-in DA converter, connected to +1.0 V power supply. Y digital outputs. YO0 is LSB. YO7 is MSB. Supply of +3.3 V power. A grounding pin. Y digital outputs. YO0 is LSB. YO7 is MSB.
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LR38266
PIN NO. SYMBOL 70 DCK1 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
IC ICU ICD ICS
I/O O - - XTO ICD O IC - IC IC IC - - IC IC IC IC IC IC IC O - - O O O O O O O O
POLARITY Clock output for YO output. A grounding pin. Supply of +3.3 V power.
DESCRIPTION
GND VDD EOO DOC HD1 ENC GND SLDI SCK SDI GND VDD ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 MCO1 VDD GND DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6
: : : :
Phase detector output comparing internal HD and HD1. Control input of YO and CO. H level sets both YO and CO high-impedance. Horizontal drive pulse generated from ENC (pin 76). Clock input to encode color signal. Internal Synchronous mode : CKI2 Line Lock mode : same as CCD clock from outside or 4 fSC. A grounding pin. Data input to set each coefficient of DSP. Clock pulse input to set SLDI data to DSP. Timing pulse input to set SLDI data to DSP. A grounding pin. Supply of +3.3 V power.
Address input to select an output data of DATA pins used in auto white balance and auto exposure. For details, see "Data Interface Timing".
Control output to update internal data stored in DSP register. Data is updated at the rising edge of MCO1. Supply of +3.3 V power. A grounding pin.
Data output to control auto white balance and auto exposure. Data of address set by ADD inputs is output. For details, see "Data Interface Timing".
100 DATA7
Input pin (CMOS level) Input pin (CMOS level with pull-up resistor) Input pin (CMOS level with pull-down resistor) Input pin (CMOS schmitt-trigger level with pulldown resistor)
DAI O TO XTO DAO
: : : : :
Input pin for DA converter Output pin Tri-state output pin Tri-state output pin DA converter output pin
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LR38266
INTERNAL COEFFICIENT TABLE
ADDRESS NAME 00h 01h STB_DA OUTPUT2 OUTPUT1 TVMD TYPE2 TYPE1 MIR ADTI1 ADTI2 APTVC APTHC CKIL MUTE_D MUTE_A 03h EOOCTRL INVSP HGCO INTL 04h EX_SXB TESYL K1 RAM_ST SEL_UV SEL_RB 06h 07h 08h CSYNCVARI BIT 6 5 4 3 2 1 0 6 5 4 3 2 1 0 4 3 2 1 0 5 4 2 1 0 8 bits Not used Standby of DA converter Output format option Output format option TV format option CCD option CCD option Image type option Input data is delayed by 1 clock cycle The clock type to input the data Vertical edge enhancement Horizontal edge enhancement Color killer function Muting digital signal outputs Muting analog signal outputs The polarity of EOO output The polarity of SP1, SP2 The polarity of HG Interlace/Non-Interlace Standby of EOO function Set YL zero in color processing Prohibited to change Standby of delay lines The option of U/V sequence CONTENTS 1 : Standby Y/C (bit 5 = 0) U/Y/V/Y (bit 5 = 1)
bit 4 = 0
bit 4 = 1 Y, U/V (bit 5 = 0) Prohibited (bit 5 = 1) 0 : NTSC 1 : PAL bit 2 = 0 bit 2 = 1 bit 1 = 0 270 k/320 k with mirror Prohibited bit 1 = 1 270 k/320 k 0 : Normal 0 : Not delayed 0 : Non-inverted 0 : ON 0 : ON 0 : ON 0 : OFF 0 : OFF 0 : Normal 0 : Normal 0 : Normal 0 : Interlace 0 : Standby 0 : OFF 0 : OFF 0 : Normal 1 : ON 1 : ON 410 k/470 k 1 : Mirror 1 : Delayed 1 : Inverted 1 : OFF 1 : OFF 1 : OFF 1 : ON 1 : ON
02h
0 : Should be kept as is
The option of R/B sequence 0 : Normal Position tuning of CSYNC with the range from +8 clock to -7 clock of CKI1.
Upper 4 bits : CSYNC, Lower 4 bits : CSYO CBLKBALI 8 bits Position tuning of CBLK with the ditto range. CBK_Y CBK_Y CBLK_C CBLK_C CBLK_UV CBLK_UV BFVARI BFVARI 7 6 5 4 3 2 1 0 The position tuning of Y-CBLK by CKI2 clock bit 6 = 0 bit 6 = 1 The position tuning of modulated C-CBLK by bit 4 = 0 CKI2 clock bit 4 = 1 The position tuning of baseband C-CBLK by CKI2 clock The position tuning of color burst signal by CKI2 clock bit 2 = 0 bit 2 = 1 bit 0 = 0 bit 0 = 1 bit 7 = 0 No tune 1 clock bit 5 = 0 No tune 1 clock bit 3 = 0 No tune 1 clock bit 1 = 0 No tune 1 clock bit 7 = 1 -1 clock -1 clock bit 5 = 1 -1 clock -1 clock bit 3 = 1 -1 clock -1 clock bit 1 = 1 -1 clock -1 clock
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LR38266
ADDRESS NAME 11h CSP_R1 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h CSP_B1 CSP_R2 CSP_B2 CB_R1 CB_R2 CB_B1 CB_B2 WB_R1 WB_R2 WB_B1 WB_B2 BIT CONTENTS 8 bits Coefficient to extract red color component 8 bits Coefficient to extract blue color component 7 bits Coefficient to tune the base level of red signal 7 bits Coefficient to tune the base level of blue signal Coefficient of the black balance of red signal 6 bits (15h) MSB : sign, other 5 bits : upper 5 bits of coefficient 8 bits (16h) lower 8 bits of coefficient 6 bits 8 bits 1 bit 1 bit Coefficient of the black balance of blue signal (17h) MSB : sign, other 5 bits : upper 5 bits of coefficient (18h) lower 8 bits of coefficient Upper coefficient to make white balance of red signal (1Ah) lower 8 bits (1Ch) lower 8 bits (MSB) sign bit (MSB) sign bit Upper coefficient to make white balance of blue signal
8 bits (19h) MSB of coefficient 8 bits (1Bh) MSB of coefficient
MAT R - Y 6 bits Coefficient of R - Y matrix MAT B - Y 6 bits Coefficient of B - Y matrix GA R - Y 6 bits Coefficient of R - Y gain GA B - Y 6 bits Coefficient of B - Y gain ENC_TI L_fsc MO_ENC MUTE_E 3 2 1 0
The clock type of encoder input Latched by fsc clock before encoding Encoding phase of PAL Muting color signal at encoder
0 : Non-Inverted 0 : Latched 0 : 4 phases 0 : Normal (MSB) sign bit (MSB) sign bit
1 : Inverted 1 : Non-latched 1 : 16/5 phases 1 : Muting
22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh
BAS R - Y 8 bits Coefficient of color burst level at R - Y BAS B - Y WBA_IP WBA_IM 8 bits Coefficient of color burst level at B - Y 8 bits Positive range of white color signal at I-axis 8 bits Negative range of white color signal at I-axis
WBA_QP 8 bits Positive range of white color signal at Q-axis WBA_QM 8 bits Negative range of white color signal at Q-axis I/Q or R - Y/B - Y WBA_SEL 2 bits Option of color signal type WB_HCL 8 bits Limiter of AWB function at higher luminance level WB_LCL 8 bits Limiter of AWB function at lower luminance level CKI_HCL 8 bits Color suppression point at higher luminance level CKI_LCL 8 bits Color suppression point at lower luminance level Luminance level to suppress color signal CKI_HLGA 8 bits Upper 4 bits : higher luminance level Lower 4 bits : lower luminance level
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LR38266
ADDRESS 2Eh NAME HT_SIG HT_1 HT_0 LT_SIG LT_1 LT_0 2Fh 30h 31h BIT 6 5 4 2 1 0 Color killer timing at lower luminance CONTENTS bit 6, bit 5, bit 4 000 : No tuning 001 Color killer timing at higher luminance 010, 011 100, 101, 110 1 clock cycle delay 2 clock cycles delay 2 clock cycles advance
111 1 clock cycle advance bit 2, bit 1, bit 0 000 : No tuning 001 1 clock cycle delay 010, 011 100, 101, 110 111 2 clock cycles delay 2 clock cycles advance 1 clock cycle advance
CKI_HECL 8 bits Horizontal aperture level to suppress color signal CKI_VECL CKI_EGA 8 bits Vertical aperture level to suppress color signal Aperture level to suppress color signal 8 bits 7 6 5 4 2 1 0 Color killer timing at horizontal transient portion Upper 4 bits : vertical aperture level Lower 4 bits : horizontal aperture level Level of edge signal 0 : 1/4 times 1 : 1 time
32h
SEL_ESFT VET_SIG VET_1 VET_0 HET_SIG HET_1 HET_0
bit 6, bit 5, bit 4 000 : No tuning 001 1 clock cycle delay Color killer timing at vertical transient portion 010, 011 100, 101, 110 111 2 clock cycles delay 2 clock cycles advance 1 clock cycle advance
bit 2, bit 1, bit 0 000 : No tuning 001 1 clock cycle delay 010, 011 100, 101, 110 111 2 clock cycles delay 2 clock cycles advance 1 clock cycle advance
33h 34h 35h 36h
CKI_LEV 5 bits Level to suppress color signal NSUP_R - Y 8 bits Coring level of R - Y signal NSUP_B - Y 8 bits Coring level of B - Y signal C_NE1 2 The polarity of color signal C_NE2 BLK_CTRL 1 0 CBLK availability at output Base level of YL signal YL_SFT1 2 bits (37h) Upper 2 bits of coefficient YL_SFT2 8 bits (38h) Lower 8 bits of coefficient YL_AMP 8 bits YL signal level to make R - Y and B - Y CGAM-A1 8 bits 1st input range of color gamma correction CGAM-A2 8 bits 2nd input range of color gamma correction CGAM-A3 8 bits 3rd input range of color gamma correction CGAM-A4 8 bits 4th input range of color gamma correction CGAM-A5 8 bits 5th input range of color gamma correction 0 : Normal 0 : ON 1 : Inverted 1 : Inverted 1 : OFF
The polarity of color signal at gamma output 0 : Normal
37h 38h 39h 40h 41h 42h 43h 44h
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LR38266
ADDRESS NAME BIT CONTENTS 45h CGAM-A6 8 bits 6th input range of color gamma correction 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 60h 61h 62h 63h 64h 65h 66h 67h 6ADV 8ADV 4DLY 2DLY 68h 1DLY HVARI 4 3 2 1 CGAM-A7 8 bits 7th input range of color gamma correction CGAM-A8 8 bits 8th input range of color gamma correction CGAM-A9 8 bits 9th input range of color gamma correction CGAM-P1 8 bits Offset of 1st straight line at color gamma correction CGAM-P2 8 bits Offset of 2nd straight line at color gamma correction CGAM-P3 8 bits Offset of 3rd straight line at color gamma correction CGAM-P4 8 bits Offset of 4th straight line at color gamma correction CGAM-P5 8 bits Offset of 5th straight line at color gamma correction CGAM-P6 8 bits Offset of 6th straight line at color gamma correction CGAM-P7 8 bits Offset of 7th straight line at color gamma correction CGAM-P8 8 bits Offset of 8th straight line at color gamma correction CGAM-P9 8 bits Offset of 9th straight line at color gamma correction CGAM-P10 8 bits Offset of 10th straight line at color gamma correction CGAM-F 1 bit Polarity of color gamma correction 0:+ CGAM-S1 8 bits Slope of 1st straight line at color gamma correction CGAM-S2 8 bits Slope of 2nd straight line at color gamma correction CGAM-S3 8 bits Slope of 3rd straight line at color gamma correction CGAM-S4 8 bits Slope of 4th straight line at color gamma correction CGAM-S5 8 bits Slope of 5th straight line at color gamma correction CGAM-S6 8 bits Slope of 6th straight line at color gamma correction CGAM-S7 8 bits Slope of 7th straight line at color gamma correction CGAM-S8 8 bits Slope of 8th straight line at color gamma correction CGAM-S9 8 bits Slope of 9th straight line at color gamma correction CGAM-S10 8 bits Slope of 10th straight line at color gamma correction SETUP 6 bits Set up level of luminance signal APT_HGA 5 bits Horizontal aperture gain APT_HCL 7 bits Coring level of horizontal aperture signal APT_VGA 5 bits Vertical aperture gain APT_VCL 7 bits Coring level of vertical aperture signal Not used VARI_MASK 4 bits Position to erase color signal by luminance mask signal 1 : 6 clocks advance of luminance signal 1 : 8 clocks advance of luminance signal 1 : 4 clocks delay of luminance signal 1 : 2 clocks delay of luminance signal 0 : No variation 0 : No variation 0 : No variation 0 : No variation 0 : No variation 1:-
0 1 : 1 clock delay of luminance signal 2 bits Position of horizontal aperture signal
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LR38266
ADDRESS NAME 69h Y_MUTE CBLK_OFF SEL_BLK Y_NEGA 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh Y_NESFT BIT 3 2 1 0 CONTENTS Muting analog luminance signal output 0 : Normal CBLK availability for luminance signal Pedestal level of luminance signal The polarity of luminance signal 0 : ON 0 : 16th step 0 : Normal
1 : Muting 1 : OFF 1 : 0 step 1 : Inverted
8 bits Base level of luminance signal Y_NEAMP 8 bits Luminance signal level MASK_NE 8 bits Masking level of luminance signal Not used Not used Not used CGAM-A1 8 bits 1st input range of color gamma correction CGAM-A2 8 bits 2nd input range of color gamma correction CGAM-A3 8 bits 3rd input range of color gamma correction CGAM-A4 8 bits 4th input range of color gamma correction CGAM-A5 8 bits 5th input range of color gamma correction CGAM-A6 8 bits 6th input range of color gamma correction CGAM-A7 8 bits 7th input range of color gamma correction CGAM-A8 8 bits 8th input range of color gamma correction CGAM-A9 8 bits 9th input range of color gamma correction CGAM-P1 8 bits Offset of 1st straight line at color gamma correction CGAM-P2 8 bits Offset of 2nd straight line at color gamma correction CGAM-P3 8 bits Offset of 3rd straight line at color gamma correction CGAM-P4 8 bits Offset of 4th straight line at color gamma correction CGAM-P5 8 bits Offset of 5th straight line at color gamma correction CGAM-P6 8 bits Offset of 6th straight line at color gamma correction CGAM-P7 8 bits Offset of 7th straight line at color gamma correction CGAM-P8 8 bits Offset of 8th straight line at color gamma correction CGAM-P9 8 bits Offset of 9th straight line at color gamma correction CGAM-P10 8 bits Offset of 10th straight line at color gamma correction 0:+ CGAM-F 1 bit Polarity of color gamma correction CGAM-S1 8 bits Slope of 1st straight line at color gamma correction CGAM-S2 8 bits Slope of 2nd straight line at color gamma correction CGAM-S3 8 bits Slope of 3rd straight line at color gamma correction CGAM-S4 8 bits Slope of 4th straight line at color gamma correction CGAM-S5 8 bits Slope of 5th straight line at color gamma correction CGAM-S6 8 bits Slope of 6th straight line at color gamma correction CGAM-S7 8 bits Slope of 7th straight line at color gamma correction CGAM-S8 8 bits Slope of 8th straight line at color gamma correction CGAM-S9 8 bits Slope of 9th straight line at color gamma correction CGAM-S10 8 bits Slope of 10th straight line at color gamma correction Not used 1:-
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LR38266
ADDRESS 8Fh A0h SEL_WBD 7 NAME BIT Not used The option of white balance data equation 0 : Accumulated data/Image area 1 : Accumulated data/Number of data The option to detect peak level to control the exposure 0 : Accumulated data of 4 pixels 1 : Accumulated data of 8 pixels The area in horizontal to detect peak level to control the exposure 0 : OFF 1 : ON The area in vertical to detect peak level to control the exposure 0 : OFF 1 : ON The area in horizontal to detect average level to control both the exposure and white balance 0 : OFF 1 : ON The area in vertical to detect average level to control both the exposure and white balance Horizontal mask signal availability 0 : OFF 0 : OFF 1 : ON 1 : ON 1 : ON CONTENTS
PEAK4_8
6
PEAHA_H PEAKA_V I_WBA_H I_WBA_V MASK_H A1h A2h A3h A4h A5h A7h A8h A9h
5 4 3 2 1
MASK_V 0 Vertical mask signal availability 0 : OFF HMSKF_U 2 bits Upper 2 bits of starting point to mask in horizontal HMSKF_L 8 bits Lower 8 bits of starting point to mask in horizontal HMSKR_U 2 bits Upper 2 bits of ending point to mask in horizontal HMSKR_L 8 bits Lower 8 bits of ending point to mask in horizontal VMSKF_U 1 bit Upper 1 bit of starting point to mask in vertical VMSKF_L 8 bits Lower 8 bits of starting point to mask in vertical VMSKR_U 1 bit Upper 1 bit of ending point to mask in vertical VMSKR_L 8 bits Lower 8 bits of ending point to mask in vertical
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LR38266
OUTPUT DATA Output Data Table
ADDRESS NAME BIT CONTENTS 00 to 07h IRIS-1-1 to 8 8 bits Average data to control exposure 08 to 0Fh IRIS-2-1 to 8 8 bits Average data to control exposure 10 to 17h IRIS-3-1 to 8 8 bits Average data to control exposure 18 to 1Fh IRIS-4-1 to 8 8 bits Average data to control exposure 20 to 27h IRIS-5-1 to 8 8 bits Average data to control exposure 28 to 2Fh IRIS-6-1 to 8 8 bits Average data to control exposure 30 to 37h IRIS-7-1 to 8 8 bits Average data to control exposure 38 to 3Fh IRIS-8-1 to 8 8 bits Average data to control exposure 40 to 43h AWBI-1-1 to 4 8 bits Average data of I/R - Y axis to control auto white balance 44 to 47h AWBI-2-1 to 4 8 bits 48 to 4Bh AWBI-3-1 to 4 8 bits 4C to 4Fh AWBI-4-1 to 4 8 bits 50 to 53h AWBQ-1-1 to 4 8 bits 54 to 57h AWBQ-2-1 to 4 8 bits 58 to 5Bh AWBQ-3-1 to 4 8 bits 5C to 5Fh AWBQ-4-1 to 4 8 bits 60h 61h 62h 63h 64h H_PEAK L_PEAK Average data of I/R - Y axis to control auto white balance Average data of Q/B - Y axis to control auto white balance Average data of Q/B - Y axis to control auto white balance
8 bits Maximum luminance signal out of 64 blocks 8 bits Minimum luminance signal out of 64 blocks
OB_DATA 8 bits Average data of optical pixels C1_OB_R 8 bits Average data of optical pixels for Mg + Ye C3_OB_B 8 bits Average data of optical pixels for Mg + Cy
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LR38266
Position of Each Output on Image Screen
(1) Luminance Signal Data to Control Exposure Left-top Side of Image
IRIS-1-1 IRIS-2-1 IRIS-3-1 IRIS-4-1 IRIS-5-1 IRIS-6-1 IRIS-7-1 IRIS-8-1 IRIS-1-2 IRIS-2-2 IRIS-3-2 IRIS-4-2 IRIS-5-2 IRIS-6-2 IRIS-7-2 IRIS-8-2 IRIS-1-3 IRIS-2-3 IRIS-3-3 IRIS-4-3 IRIS-5-3 IRIS-6-3 IRIS-7-3 IRIS-8-3 IRIS-1-4 IRIS-2-4 IRIS-3-4 IRIS-4-4 IRIS-5-4 IRIS-6-4 IRIS-7-4 IRIS-8-4 IRIS-1-5 IRIS-2-5 IRIS-3-5 IRIS-4-5 IRIS-5-5 IRIS-6-5 IRIS-7-5 IRIS-8-5 IRIS-1-6 IRIS-2-6 IRIS-3-6 IRIS-4-6 IRIS-5-6 IRIS-6-6 IRIS-7-6 IRIS-8-6 IRIS-1-7 IRIS-2-7 IRIS-3-7 IRIS-4-7 IRIS-5-7 IRIS-6-7 IRIS-7-7 IRIS-8-7 IRIS-1-8 IRIS-2-8 IRIS-3-8 IRIS-4-8 IRIS-5-8 IRIS-6-8 IRIS-7-8 IRIS-8-8
(2) Color Signal Data to Control Auto White Balance Left-top Side of Image
AWBI/AWBQ-1-1 AWBI/AWBQ-2-1 AWBI/AWBQ-3-1 AWBI/AWBQ-4-1 AWBI/AWBQ-1-2 AWBI/AWBQ-2-2 AWBI/AWBQ-3-2 AWBI/AWBQ-4-2 AWBI/AWBQ-1-2 AWBI/AWBQ-2-2 AWBI/AWBQ-3-2 AWBI/AWBQ-4-2 AWBI/AWBQ-1-2 AWBI/AWBQ-2-2 AWBI/AWBQ-3-2 AWBI/AWBQ-4-2
Either I or R - Y is selectable by address 28h. Either Q or B - Y is selectable by address 28h.
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LR38266
ABSOLUTE MAXIMUM RATINGS
PARAMETER Power supply voltage Input voltage Output voltage Storage temperature SYMBOL VDD VI VO TSTG RATING -0.3 to +4.6 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 UNIT V V V C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Power supply voltage Operating temperature Input clock frequency SYMBOL VDD TOPR fCK MIN. 3.0 -20 TYP. 3.3 +25 28.6 MAX. 3.6 +70 UNIT V C MHz
ELECTRICAL CHARACTERISTICS
PARAMETER Input "Low" voltage Input "High" voltage Input "Low" voltage Input "High" voltage Hysteresis voltage Output "Low" voltage Output "High" voltage Output leakage current Output "Low" voltage Output "High" voltage Output leakage current Input "Low" current Input "High" current Output "Low" voltage Output "High" voltage Resolution Linearity error Differential error Full scale current Reference voltage Reference resistance Output load resistance SYMBOL VIL VIH VT- VT+ VT+ - VT- VOL1 VOH2 |IOZ| VOL1 VOH2 |IOZ| |IOL1| |IOH2| VOL1 VOH2 RES EL ED |IFS| VREF RREF ROUT
6. 7. 8. 9. 10.
(VDD = 3.30.33 V, TOPR = -20 to +70 C)
CONDITIONS MIN. 0.8VDD 0.8VDD 0.2 IOL = -1.6 mA IOH = 0.8 mA High-impedance IOL = -1.6 mA IOH = 0.8 mA High-impedance VIN = 0 V VIN = VDD IOL = -1.6 mA IOH = 0.8 mA VREF = 1.0 V RREF= 4.8 k$ ROUT = 75 $ 13 1.0 4.8 75
Applied Applied Applied Applied Applied to to to to to input (ICD). output (O). outputs (YENCO, CENCO). input (VREF). inputs (IREF1, IREF2).
TYP.
MAX. UNIT 0.2VDD V V 0.2VDD V V V 0.1VDD V V A V V 1.0 A A 0.1VDD A V V Bit 3.0 1.0 LSB LSB mA V k$ $
NOTE 1
2
0.9VDD -1.0 0.9VDD -1.0 10 10 0.9VDD 8 1.0 0.1VDD
3
4 5 6 7
8
9 10 8
NOTES :
1. 2. 3. 4. 5. Applied Applied Applied Applied Applied to to to to to inputs (IC, ICD, ICU). input (ICS). output (TO). output (XTO). input (ICU).
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LR38266
Data Interface Timing
Data is stored in LR38266 SLDI SCK MSB SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB LSB
Address SCK should be slower than 20 MHz.
Data
Data Input
ADD [6 : 0]
DATA [7 : 0]
MAX. 47 ns
Data output in 47 ns or more after address input is valid.
Data Output
16
LR38266
DETAIL EXPLANATION CCD
CCD type out of 270 k, 320 k, 410 k and 470 k pixels is selected by address 01h.
Output Signal Format
(1) Analog Video Signal Output Built-in DA converters output luminance (Y) signal without CSYNC and modulated color signal of NTSC or PAL. Standby mode of DA converter makes DA output pins high impedance. (2) Digital Video Signal Output (address 01h) One out of three formats below is selectable by address 01h. High level of pin 74 as DOC makes all digital output pins high impedance. 1. 8-bit Y and 8-bit C 2. 8-bit Y and 8-bit U/V 3. 8-bit U/Y/V/Y
(3) Black Balance Control Data Output (3 data with 8 bits) Three kinds of outputs below are at DATA output pins. * An average signal of CCD optical black portion consisting of 4 pixels per horizontal line for 128 horizontal lines located in the image center. * An average signal of CCD optical black portion consisting of 2 pixels per horizontal line for 128 horizontal lines located in the image center, which is available to tune the base level of Mg + Ye color signal component. * An average signal of CCD optical black portion consisting of 2 pixels per horizontal line for 128 horizontal lines located in the image center, which is available to tune the base level of Mg + Cy color signal component.
Camera Signal Processing
(1) Optical Black Signal Clamping The optical black signal portion is clamped so as to be 64h by using the average level of the input digital signal. The averaging is done for every field. (2) Horizontal Period Delay Line There are two horizontal delay lines in this IC for camera signal processing. (3) Digital Filter for Luminance Signal These are low-pass filters to make a Y signal from the color CCD signal. (4) Gamma Correction for Luminance Signal 10-bit input signal is converted into an 8-bit signal with a gamma curve defined by 10 straight lines. Slope and position of every straight line can be set by address. (5) Edge Enhancement of Luminance Signal After gamma correction, the edge of the luminance signal is enhanced in both horizontal and vertical. How to enhance is tunable by address.
Camera Control Data Output
(1) Exposure Control Data Output (64 data with 8 bits and 2 data with 8 bits) The user-defined image area consists of 64 blocks divided into 8 x 8 blocks. Each average luminance level is output to DATA output pins by setting ADD input pins. In the defined area, the maximum luminance level and the minimum luminance level are output to DATA output pins. (2) White Balance Control Data Output (two kinds of 16 data with 8 bits) The user-defined image area consists of 16 blocks divided into 4 x 4 blocks. Average color signal levels of either both I and Q or both R - Y and B - Y are output to DATA output pins by setting ADD input pins.
17
LR38266
(6) Set-up Level of Luminance Signal The set-up level is tunable by address. (7) Polarity Option and Level Tuning of Luminance Signal The polarity of the input signal from the AD converter can be inverted before filtering. The DC offset level and the amplitude are tunable by address. (8) Masking Luminance Signal The restricted area in the whole image can be set by address. The exposure function and the auto white balance function can be used only in the restricted area. (9) Extract of Color Signal Component Color signal components are extracted by following processing calculation. Red = (Mg + Ye) - K1 (G + Cy) Blue = (Mg + Cy) - K2 (G + Ye) YL = ((Mg + Ye) + (G + Cy) + (Mg + Cy) + (G + Ye))/4 K1 and K2 are variable by address. (10) Digital Filter of Color Signal Component Red, blue and YL are passed to limit each bandwidth so as to be half of extracted signals by low-pass filters. (11) Black Level Clamping of Color Signal Component The black level of red and blue signals can be tuned by address 15h, 16h, 17h, and 18h. (12) White Balance The amplitude of red and blue signals can be tuned by address 19h, 1Ah, 1Bh, and 1Ch for white balance situation. (13) Color Gamma Correction 10-bit input signal of red, blue and YL signals are converted into an 8-bit signal with gamma curve defined by 10 straight lines. The slope and position of every straight line can be set by address. (14) Color Matrix Correction Color rendition can be tuned by address 1Dh and 1Eh under below equation. R - Y = (R - Y) + K1 (B - Y) B - Y = (B - Y) + K2 (R - Y) (15) Color Level Adjustment The amplitude of R - Y and B - Y can be tuned by address 1Fh and 20h. (16) Color Level Suppression A false color signal at both the transient portion of luminance signal and the high-light portion of luminance signal can be suppressed by address 2Bh, 2Ch, 2Dh, 2Eh, 30h, 31h, 32h, 33h, 34h and 35h. (17) Polarity Option and Level Tuning of Color Signal The polarity of the color component signal can be inverted before gamma correction. The DC offset level and the amplitude are tunable by address 36h, 37h, 38h and 39h. (18) NTSC/PAL Color Signal Encoder R - Y and B - Y color signals are modulated under NTSC or PAL format. Modulated clock frequency and TV format are selected by address 03h, 21h, 22h and 23h. Line-lock system requires the clock generator outside LR38266. (19) Accumulator to Control Exposure Three kinds of output data below become available by address A0h, 00h to 3Fh, 60h and 61h. * Average signal in either the whole image or restricted area. * Maximum signal in either the whole image or restricted area. * Minimum signal in either the whole image or restricted area.
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LR38266
(20) Accumulator to Control White Balance Output data below become available by address 24h, 25h, 26h, 27h, 28h, 29h, 2Ah, A0h and 4Fh to 5Fh. Average signal of I (R - Y) and Q (B - Y) in 16 areas of the whole image. These data can be weighted by both the color zone of I-axis and/or Q-axis and the range of luminance. (21) Accumulator to Control Color Black Balance Average signal of the optical black portion to clamp the black level of color signal is available by address 62h, 63h and 64h. (22) Others * The output timing of synchronous signals are available by address 06h, 07h and 08h. * Functions like standby, muting, etc. are available by address 01h, 03h, 04h and 21h.
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PACKAGES FOR CCD AND CMOS DEVICES
PACKAGE
100 LQFP (LQFP100-P-1414)
0.5TYP. 75 76 0.20.08 51 50 0.08 (1.0) M 0.1250.05
(Unit : mm)
Unit : mm
14.00.2
16.00.3
100 1 (1.0) 14.00.2 16.00.3 25
26 (1.0)
(1.0 )
0.6375 1.70MAX. 1.40.2 0.10.1
20
Package base plane
15.00.2
0.1

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